The LSTTLMSI SN5474LS139 is a high speed Dual 1- of- 4 DecoderDe- multiplexer. This device is ideally suited for high speed 7432 bipolar memory chip select address decoding. The device has two independent decoders each accepting two inputs . The 74HC32; 74HCT32 is a quad 2- input OR gate. Download Description & parametrics Technical documents Tools & software.
74139 ic datasheet 7432. Quad 2- input positive- OR gates Datasheet. Quadruple 2- Input Positive- OR Gates datasheet. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. com Datasheet ( data sheet) search for integrated circuits ( ic) transistors , other electronic components such as resistors, capacitors, semiconductors diodes. IC datasheet The 74LS138 is a high speed 1- of- 8 Decoder/ Demultiplexer. 74139 datasheet pdf 74139 datasheet pdf.
7432 Quad 2- Input OR Gate Components datasheet pdf data sheet FREE from Datasheet4U. 74139 7432 datasheet pdf.
74LS139 2- to- 4 Line Decoder/ Demultiplexer TTL IC Features: Two Independent Two- of- Four Decoders Based Upon the Select Inputs Inputs Clamped with Schottky Diodes Designed for Memory Decoders and Data Transmission Systems Operating Temperature up to 70oC Standard TTL Switching Voltages See full feature at datasheet from below:. 14- Lead Small Outline Integrated Circuit ( SOIC), JEDEC MS- 120, 0. Complete Datasheet of IC 7432 chapter ( including extra questions, long questions, short questions, mcq) can be found on EduRev, you can check out lecture & lessons summary in the same course for Syllabus. DM74LS153 Dual 1- of- 4 Line Data Selectors/ Multiplexers Physical Dimensions inches ( millimeters) unless otherwise noted ( Continued) 16- Lead Plastic Dual- In- Line Package ( PDIP), JEDEC MS- 001, 0. 300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and. General description.
74139 ic datasheet 7432
The 74HC139; 74HCT139 decodes two binary weighted address inputs ( nA0, nA1) to four mutually exclusive outputs ( nY0 to nY3). Each decoder features an enable input ( nE). When nE is HIGH all outputs are forced HIGH.